Logic and transistor circuit verification using regression testing and hierarchical recursive learning /
can handle all of those circuits, and are almost always
| Main Author: | |
|---|---|
| Format: | Thesis eBook |
| Language: | English |
| Published: |
[Place of publication not identified] :
[publisher not identified] ;
1996.
|
| Subjects: | |
| Online Access: | Link to OAKTrust copy |
| Summary: | can handle all of those circuits, and are almost always combinational logic circuits, and their switch-level faster. ISCASS5 benchmarks. Unlike most other approaches, Verifast techniques. A prototype of a verification tool, Verifast, testing, hierarchical recursive learning, and test generation transistor implementation. Our approach CODibines regression Verifast on optimized and technology-mapped versions of the was developed based on this approach. We demonstrate We describe a new approach for formal verification of |
|---|---|
| Item Description: | "Major subject: Computer Science". Vita. |
| Physical Description: | ix, 51 leaves : illustrations ; 28 cm. Also available online. Issued also on microfiche from Lange Micrographics. |
| Bibliography: | Includes bibliographical references. |