IC performance prediction system /
and in-situ data to make performance predictions. Based on
| Main Author: | |
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| Format: | Thesis eBook |
| Language: | English |
| Published: |
[Place of publication not identified] :
[publisher not identified] ;
1996.
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| Subjects: | |
| Online Access: | Link to OAKTrust copy |
| Summary: | and in-situ data to make performance predictions. Based on and when the chip is to be packaged away from the foundry, be selected according to how a chip will be binned. Binning is the placement of chips into several different circuit pack-age makes up a large fraction of total product cost, and has a major influence on product performance and data available at the time each decision must be made. For difficulty in achieving these goals is that there is limited done after the water-level electrical test, but the water done on the basis of performance (e.g. ,speed, operating example, performance banning and package selection must be for process diagnosis purposes. We will use the predicted In a mixed-product semiconductor foundry, optimization of meet product demand. This can be coupled with equipment parametric electrical test data, supplemented with in-line performance in order to select the appropriate package. Performance prediction is also important for product control performance prediction system (IPPS) proposed in this performance to determine additional wafer starts necessary to practice is to accept some loss of profits due to imperfect Predictions that fall outside acceptable limits will be used predictions that result in under-specified and over-packaged product binning, packaging, product quantity control and product supply and demand, or additional yield loss. The IC products, additional failures in final test, a mismatch of range). For maximum profit, it must be accurately determined rapid problem diagnosis are all critical to economic success. reliability. To minimize packaging costs, packaging has to research will use primarily wafer-level functional and specification categories. Binning has traditionally been such as when it will be used in Multi-Chip Module (MCM). The test is not a thorough performance test. The current the waterlevel parametric test, we will predict chip utilization to predict and minimize fabrication costs. which specification bin a chip ties in. The integrated |
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| Item Description: | "Major subject: Electrical Engineering". Vita. |
| Physical Description: | xi, 58 leaves : illustrations ; 28 cm. Also available online. Issued also on microfiche from Lange Micrographics. |
| Bibliography: | Includes bibliographical references. |