Timing analysis of logic=level digital circuits using uncertainty intervals /
aggressive timing constraints inherent in high performance
| Main Author: | |
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| Format: | Thesis eBook |
| Language: | English |
| Published: |
[Place of publication not identified] :
[publisher not identified] ;
1996.
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| Subjects: | |
| Online Access: | Link to OAKTrust copy |
| Summary: | aggressive timing constraints inherent in high performance analysis is increasingly used to deal with the more analysis procedure is developed. Several techniques are blocked paths early and guide the search toward the true checking of multiple paths with equivalent constraints. The Competitive design of modem digital circuits requires high designs and the increased complexity of current VLSI during path generation. The use of Recursive Learning to during timing analysis. In this work, an incremental timing Dynamic dominators are introduced and used to prevent the elements. The delay of the circuit elements is dependent on find indirect conflicts during the path building is studied. In addition, an improved dynamic sensitization criteria is incremental path generation routine. introduced to improve the implicit trimming of false paths is used to incorporate these variations of delay into the longest path. These techniques are shown to improve the occurrence of non-functional paths which must be dealt with path elimination techniques and the improved dynamic performance at reduced cost and time-to-market. Timing presented which incorporates the actual delay of circuit reduce cost and time-to-market has resulted in increased represent transitions in the circuit since the exact time of results on some combinational benchmark circuits. search process during the path building phase of the sensitization criteria is demonstrated through experimental sensitization criteria. An uncertainty interval is used to technique of forward trimming is developed to discover technology. Reliance on synthesis and modular design to the manufacturing process parameters. A min/max delay model the transition is unknown. The performance of the implicit Timing Analysis of Logic-Level Digital Circuits Using |
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| Item Description: | "Major subject: Computer Science". Vita. |
| Physical Description: | ix, 58 leaves : illustrations ; 28 cm. Also available online. Issued also on microfiche from Lange Micrographics. |
| Bibliography: | Includes bibliographical references. |