APA (7th ed.) Citation

Bell, J. A. (1996). Timing analysis of logic=level digital circuits using uncertainty intervals. [publisher not identified].

Chicago Style (17th ed.) Citation

Bell, Joshua Asher. Timing Analysis of Logic=level Digital Circuits Using Uncertainty Intervals. [Place of publication not identified]: [publisher not identified], 1996.

MLA (9th ed.) Citation

Bell, Joshua Asher. Timing Analysis of Logic=level Digital Circuits Using Uncertainty Intervals. [publisher not identified], 1996.