Hypercube based distributed shared memory multiprocessors /
Due to ever increasing demand on computation power and having reached the physical speed up limitations of uniprocessor based computers, all the major computer vendors have started designing multiprocessors. Multiprocessors can be broadly classified into shared memory and message passing. Shared m...
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| Format: | Thesis Book |
| Language: | English |
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[Place of publication not identified] :
[publisher not identified] ;
1995.
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| Online Access: | http://proxy.library.tamu.edu/login?url=http://proquest.umi.com/pqdweb?did=742744941&sid=1&Fmt=2&clientId=2945&RQT=309&VName=PQD |
| Summary: | Due to ever increasing demand on computation power and having reached the physical speed up limitations of uniprocessor based computers, all the major computer vendors have started designing multiprocessors. Multiprocessors can be broadly classified into shared memory and message passing. Shared memory ones are more popular due to the ease of programming and the availability of parallelizing compilers. For small scale systems a bus has been used successfully for connecting the processors together. For the system to be scalable, other networks such as MIN, Mesh, Hypercube etc. have to be used. Among these hypercube has been used for many multiprocessor designs. When a point to point network is used for shared memory the memory access time is reduced by using caches near each processor. In such a situation directories are used for maintaining cache coherence. Several "limited directory" schemes have been proposed, which limit the directory storage overhead but result in increased memory access latencies. In this dissertation we develop a hypercube based shared memory multiprocessor with caches close to each processor. Efficient cache coherence mechanisms are developed, which decrease the storage overhead as well as the memory access latencies. For small size system a single ring is embedded into the hypercube and is used for broadcasting the invalidation messages. And to make the proposed architecture scalable, multiple rings connected in an hierarchical fashion are used. A detailed cache coherence scheme is developed for the two configurations. Communication in the network is made efficient by using the ring as well as e-cube routing. Wormhole routing along with messages traveling on a logically embedded ring provide a snoopy behavior to the proposed schemes. A synthetic trace driven simulation package is developed for evaluating the complete operating range. This package is further extended to real applications by using an existing parallel compiler and porting several applications to our system. We show, with the help of the simulation results that our techniques perform as well as, if not better than full map directory scheme. |
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| Item Description: | Vita. "Major Subject: Computer Science". |
| Physical Description: | xiv, 134 leaves : illustrations ; 28 cm. Issued also on microfiche from University Microfilms Inc. |
| Bibliography: | Includes bibliographical references. |