Comprehensive functional testing and dynamic compensation techniques for Cellular Neural Networks /
additional hardware, and are limited to specific topologies. The
| Main Author: | |
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| Format: | Thesis eBook |
| Language: | English |
| Published: |
[Place of publication not identified] :
[publisher not identified] ;
1995.
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| Subjects: | |
| Online Access: | Link to OAKTrust copy |
| Summary: | additional hardware, and are limited to specific topologies. The and system offsets. Whenever possible, the compensation arrays independent of the size or topology of the array. The Cellular Neural Networks (CNN's) are analog, non-linear, dynamic characterize and attempt to minimize or eliminate the effect conduct functional testing and dynamic compensation of CNN different complexities, combine input stimulus files in a fabricated in sub-micron Very Large Scale Integration (VLSI) functionality of CNN'S. Present techniques for testing CNN goal of this thesis is to provide a deterministic method to hardware provide only limited capabilities, often require in real CNN hardware. The functional tests consist of a independently, otherwise a global compensation approach is logical manner, and generate the necessary files for methods provide comprehensive, non-invasive techniques for mismatches, non-linearity in the multipliers and state nodes, need to develop robust testing methods to establish baseline of software tools was developed to select CNN macromodels of of undesirable parametric faults such as time-constant output vector set. The dynamic compensation strategies propagated to the output where it is compared to a known good provide insight into different problems faced when testing a refine, and measure the effectiveness of the proposed testing sequence of inputs to the array that insure each node in the simulation. The simulation results were used to design, strategies. system level representation of the CNN is toggled and systems which are especially well suited for solving problems in techniques are carried out locally on each cell technologies. The increase in circuit integration has driven the the areas of image processing and pattern recognition. State of the art implementations of two-dimensional CNN's arrays are used. Numerous CNN architectures had to be modeled to verifying the integrity of each of the functional paths as VLSI implementations of CNN arrays. For this reason, a set well as procedures to measure and minimize parametric faults |
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| Item Description: | "Major subject: Electrical Engineering". Vita. |
| Physical Description: | xiv, 127 leaves : illustrations ; 28 cm. Also available online. Issued also on microfiche from Lange Micrographics. |
| Bibliography: | Includes bibliographical references. |