Communication hardware and algorithms for high-speed networks /
We develop two new switch architectures, DbDest and Pdl-
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| Format: | Thesis Book |
| Language: | English |
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[Place of publication not identified] :
[publisher not identified] ;
1995.
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| Subjects: | |
| Online Access: | http://proxy.library.tamu.edu/login?url=http://proquest.umi.com/pqdweb?did=742535341&sid=1&Fmt=2&clientId=2945&RQT=309&VName=PQD |
| Summary: | We develop two new switch architectures, DbDest and Pdl- DbDest , that can offer multiple paths from each input to each output with small hardware cost and are able to support a wide range of services with diverse traffic characteristics. Our simulations show that DbDest and Pdl- DbDest can accomplish the same or better performance than existing switching architectures but with only half the hardware cost of the parallel banyan networks. As the DbDest or Pdl-DbDest network size increases, the performance-cost ratio improves. By incorporating a link grouping technique, and by using an efficient multilink access algorithm, we further reduce cell loss, and increase throughput, especially in extremely bursty traffic environment. We investigate the fault tolerance aspect of DbDest and Pdl-DbDest, and propose cost-efficient methods to place redundant switch components to make the fabrics recover from single or multiple failures. Also, a set of fixed-number test vectors is generated to detect and locate any single or multiple faults in DbDest. Moreover, we show that Pdl-DbDest is highly scalable, and is suited for very large scale switch implementation. With the aid of advanced design tools, like VHDL, logic compilers, and simulators , the implementation of DbDest or Pdl-DbDest is feasible by using BICMOS (or CMOS) VLSI implementation and by using a three-dimensional modular packaging structure to easily achieve the speed of 155 Mb/s, or even 622 Mb/s. In this dissertation, we also propose a high-performance buffer management scheme in which finite input queues and virtual output queues are used with a speedup factor of one in a non- blocking switching network to emulate the output queueing performance. Since we only use a speed-up factor equal to one, the hardware cost significantly decreases, yet the performance remains close to that of output queueing. We show that only a sorting network is needed, and there is no need to use a routing network. Furthermore, the performance of the proposed buffer scheme is not sensitive to the network size N. We estimate the hardware cost for the proposed buffer scheme, and compare the performance with other existing schemes. We also propose a two-stage-input-buffered scheme to further improve the cell loss rate under medium traffic offerload. We develop an analytical model for our buffer scheme, and present simulation results for priority and non- priority services. Moreover, we propose a priority service algorithm that improves the delay for low-priority cells without a significant increase in the delay for high-priority cells. |
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| Item Description: | Vita. "Major Subject: Electrical Engineering". |
| Physical Description: | xiv, 160 leaves : illustrations ; 28 cm. Issued also on microfiche from University Microfilms Inc. |
| Bibliography: | Includes bibliographical references. |