Modeling fault tolerance and testing for complex digital systems /
To meet the increasing demand of system reliability and availability, fault-tolerant techniques have been widely employed in today's complex digital systems. This dissertation studies novel modeling issues for fault tolerance and testing in large digital systems. New analytical models for eva...
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| Format: | Thesis Book |
| Language: | English |
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[Place of publication not identified] :
[publisher not identified] ;
1995.
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| Online Access: | http://proxy.library.tamu.edu/login?url=http://proquest.umi.com/pqdweb?did=742534981&sid=1&Fmt=2&clientId=2945&RQT=309&VName=PQD |
| Summary: | To meet the increasing demand of system reliability and availability, fault-tolerant techniques have been widely employed in today's complex digital systems. This dissertation studies novel modeling issues for fault tolerance and testing in large digital systems. New analytical models for evaluating intermediate tests for yield enhancement and quality assurance of systems manufactured using fault-tolerant multichip modules (MCMS) for massively parallel computing (MPC) are presented. Unlike a previous method, our approach can employ intermediate tests to meet MCM quality requirements effectively. In addition, efficient test strategies employing intermediate tests for fault-tolerant MCMs are proposed and analyzed. Our results show that a yield-analysis model employing the LRTWS (least recently tested in working-test-set) test strategy proposed in this dissertation may provide a very good figure of merit due to its cost, delivery, number of tests and reliability benefits for current technology. New optimal design strategies for cost-effectiveness and on-time delivery of fault tolerant MCMs for MPC are presented. In the proposed approach, we analyze the effect of residual redundancy on operational reliability of fault-tolerant MCMS. Our results show that our approach can be applied to design optimal MCMs for MPC applications more efficiently, subject to yield and reliability constraints, thus signif icantly improving cost-effectiveness in manufacturing and ensuring on-time delivery of the entire MPC system. Analytical and simulation models for evaluating the operation of a uniprocessor which utilizes a time redundant approach for fault-tolerant computing are presented. In the proposed approach, we consider time redundancy in the uniprocessor as a last alternative once all spares are used. The modified triple time redundant scheme (MTTRS) presented here not only can mask single transient faults, but it also detects double transient faults with virtually no degradation of response time. Several policies for appropriately scheduling the three versions of the jobs in the MTTRS are also proposed and analyzed. Our results show that for moderately loaded systems, the computation of the extra versions of a job may not significantly affect the response time of the first version by choosing an appropriate scheduling method. |
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| Item Description: | Vita. "Major Subject: Computer Science". |
| Physical Description: | xi, 117 leaves : illustrations ; 28 cm. Issued also on microfiche from University Microfilms Inc. |
| Bibliography: | Includes bibliographical references. |