Design and test of programmable interconnects for digital systems /
The high density technologies such as VLSI, MCM and WSI has made possible the implementation of complex digital systems. This has been accomplished using modularity in design and manufacturing. These technologies utilize a modular replication of the processing elements and a homogeneous interconnec...
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| Format: | Thesis Book |
| Language: | English |
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[Place of publication not identified] :
[publisher not identified] ;
1995.
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| Online Access: | http://proxy.library.tamu.edu/login?url=http://proquest.umi.com/pqdweb?did=742535021&sid=1&Fmt=2&clientId=2945&RQT=309&VName=PQD |
| Summary: | The high density technologies such as VLSI, MCM and WSI has made possible the implementation of complex digital systems. This has been accomplished using modularity in design and manufacturing. These technologies utilize a modular replication of the processing elements and a homogeneous interconnection network, through the programming of the system interconnects. However, costs for manufacturing as well as tailoring a general architecture to particular applications for full customization have increased and thus, it has become a major issue. Switch programming is dependent on the switching circuitry and the routing approach which is employed for generating the new topology of the system. Reconfiguration must provide fault and defect tolerance in the processing elements and the interconnections. The high density and complexity of these systems require that testing and diagnosis must be efficiently implemented to diagnose the occurrence of faults due to either a short, or open in nets. This dissertation addresses the following issues related to programmable interconnects in large digital systems: (1) reducing the programming cost of routing for switch programming in reconfigurable 2D arrays. (2) developing routing techniques for switch programming by using different switch structures in reconfigurable array systems. (3) designing a fault-tolerant router for signal distribution in wafer scale integration (WSI) architectures. (4) developing strategies for testing interconnects, including field programmable interconnect chips (FPICs), by taking into account the layout. Based on redundancy reduction and relaxation techniques, cost optimization procedures are proposed for reducing the programming cost of routing in reconfigurable arrays. A switch structure that has a concurrent capability is investigated and an efficient algorithm is proposed to utilize the soft switch design and heuristically reduce the cost. The problem of designing an optimal fault-tolerant (homogeneous) router for redundant path signal routing is also discussed and an algorithm is developed to determine the placement of the switches in the router that satisfies optimality. A new approach is proposed that initially utilizes the principles of the walking-1 test set together with the adjacency and continuous assumptions to construct a test set of smaller cardinality by taking into account the layout. |
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| Item Description: | Vita. "Major Subject: Computer Science". |
| Physical Description: | xiv, 126 leaves : illustrations ; 28 cm. Issued also on microfiche from University Microfilms Inc. |
| Bibliography: | Includes bibliographical references. |