Pseudo random routing reconfiguration using a dedicated switching network for VLSI/WSI multi-processor array systems /
| Main Author: | |
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| Format: | Thesis Book |
| Language: | English |
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[Place of publication not identified] :
[publisher not identified] ;
1995.
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| Subjects: | |
| Online Access: | http://proxy.library.tamu.edu/login?url=http://proquest.umi.com/pqdweb?did=742535161&sid=1&Fmt=2&clientId=2945&RQT=309&VName=PQD |
| Item Description: | Vita. "Major Subject: Electrical Engineering". |
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| Physical Description: | x, 94 leaves : illustrations ; 28 cm. Issued also on microfiche from University Microfilms Inc. This research introduces and implements the reconfiguration for multi-processor array system fault tolerance which adopts the dedicated switching network. Since redundancy was adopted for fault tolerance of multi-processor array systems, the various reconfigurations have been studied. All the methodologies have focused on utlization of spare processor elements and decreasing hardware complexity, increasing and resulted in designing the cost effective system. This research utilizes a dedicated switching network which connects separately located spare PEs and operational PEs. If the switching network is not blocked, the availability of spare PEs can be 100%. In this research, the one-sided (folded) type switching network is adopted to keep its regularity. In addition, the growing of the network size up to processor array size can be easily done by using a one-sided switching network. The placement and routing for reconfiguration are performed only by the switching network itself. This means that there is no central controller and algorithms needed for fault tolerance. Besides, by using the dedicated switching network which has the nature of the distributed control, this reconfiguration technology can be adopted to any type of the multiprocessor array systems, such as SISD, SIMD, MISD, and MIMD, with no restriction. Since this research uses only internal track switches in the processor elements for intercommunication between PEs, the delay time and complexity, by track switches or multiplexers between all the PEs, are reduced. Moreover, the internal switch is known for its low probability of fault and its simple structure. The dedicated switching network does free search for the routing and placement to substitute faulty PEs for itself without any help from other devices (for example, error signal controller). Therefore, all other PEs except the faulty one do not have to wait for the completion of the reconfiguration. Instead they can concentrate on their own original works. |
| Bibliography: | Includes bibliographical references. |