Effect of resolved branches on the performance of delayed branching /
(Model 2). A comparison of these two models yields the
| Main Author: | |
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| Format: | Thesis eBook |
| Language: | English |
| Published: |
[Place of publication not identified] :
[publisher not identified] ;
1995.
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| Subjects: | |
| Online Access: | Link to OAKTrust copy |
| Summary: | (Model 2). A comparison of these two models yields the and the other without delayed branching for resolved branches Benchmark programs are run to obtain results regarding the branch instructions with some useful instructions. This brief introduction to the performance effects of branches is followed by a description of the implementation details. instruction-issue superscalar pipelined RISC processor. Two of the delayed branching scheme is studied for a two- outperform Model 2 for all benchmarks. It is concluded that performance implications of resolved branch instructions. A performance issues related to delayed branching. performance of the delayed branching scheme. It is often possible to fill up the delay slots occurring due to resolved processor models are created in Verilog HDL, one with recommends that resolved branches be considered for all resolved branches do play a significant role in the resolved branches using delayed branching scheme (Model 1) The impact of resolved branch instructions on the performance throughputs offered by the two models. Model 1 is found to |
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| Item Description: | "Major subject: Electricsl Engineering". Vita. |
| Physical Description: | ix, 84 leaves : illustrations ; 28 cm. Also available online. Issued also on microfiche from Lange Micrographics. |
| Bibliography: | Includes bibliographical references. |