http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
Design of a multithreaded data cache for a hyperscalar processor
A multithreaded data cache for a hyperscalar processor is
another. The miss penalty is reduced by using a data
cache can support one outstanding request per thread. So,
cache is lockup-free or non-blocking which allows it to serve
carried out to optimize the cache for this high performance
designed and optimized in this study. The data cache can
each cycle. It is assumed that the multithreaded processor
forwarding technique which will forward the missed data to
Hardware Description Language. Trace-driven simulation is
model of the data cache is developed by using Verilog
only one new request from one thread will not be generated
separate requests from different threads at each cycle. The
single thread at each cycle and then it switches to another
support two simultaneous requests from a single thread at
the CPU as soon as the cache fetches it from memory. The
the request from one thread while servicing the misses from
thread and repeats the operation. The data cache can handle
unless the previous request has been satisfied. A simulation
using the data cache can generate at most two requests from a
"Major subject: Electrical Engineering".
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