Design of a multithreaded data cache for a hyperscalar processor /
A multithreaded data cache for a hyperscalar processor is
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| Format: | Thesis eBook |
| Language: | English |
| Published: |
[Place of publication not identified] :
[publisher not identified] ;
1995.
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| Subjects: | |
| Online Access: | Link to OAKTrust copy |
| Summary: | A multithreaded data cache for a hyperscalar processor is another. The miss penalty is reduced by using a data cache can support one outstanding request per thread. So, cache is lockup-free or non-blocking which allows it to serve carried out to optimize the cache for this high performance designed and optimized in this study. The data cache can each cycle. It is assumed that the multithreaded processor forwarding technique which will forward the missed data to Hardware Description Language. Trace-driven simulation is model of the data cache is developed by using Verilog only one new request from one thread will not be generated processor. separate requests from different threads at each cycle. The single thread at each cycle and then it switches to another support two simultaneous requests from a single thread at the CPU as soon as the cache fetches it from memory. The the request from one thread while servicing the misses from thread and repeats the operation. The data cache can handle unless the previous request has been satisfied. A simulation using the data cache can generate at most two requests from a |
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| Item Description: | "Major subject: Electrical Engineering". Vita. |
| Physical Description: | xi, 80 leaves : illustrations ; 28 cm. Also available online. Issued also on microfiche from Lange Micrographics. |
| Bibliography: | Includes bibliographical references. |