Design and analysis of instruction issue logic for hyperscaler processors /
A dynamic instruction scheduling mechanism developed is
| Main Author: | |
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| Format: | Thesis eBook |
| Language: | English |
| Published: |
[Place of publication not identified] :
[publisher not identified] ;
1995.
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| Subjects: | |
| Online Access: | Link to OAKTrust copy |
| Summary: | A dynamic instruction scheduling mechanism developed is another hyperscalar scheduling mechanism is estimated. The between the processor throughput and resource utilization. cost-performance ratio of the two schemes are analyzed. dependencies by dynamically assigning a tag during Destination registers are renamed to avoid anti and output evaluate the scheme is presented. The model is capable of fetched in to a central window to improve the processor handling variable number of threads, functional units, window instruction decode. Instructions from multiple streams are instructions fetched. The cost of the proposed scheme and presented. The proposed mechanism works out a compromise processor throughput and resource utilization when the proposed scheme is used. Simulation results show a substantial increase in the sizes, operand buses, write ports and the number of The scheduling mechanism issues instructions out of order. throughput. A hyperscalar processor model developed to |
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| Item Description: | "Major subject: Electrical Engineering". Vita. |
| Physical Description: | x, 70 leaves : illustrations ; 28 cm. Also available online. Issued also on microfiche from Lange Micrographics. |
| Bibliography: | Includes bibliographical references. |