C-testable ILAs and Built-In Self Test /
The synthesis of array specific Built-In Self Test (BIST)
| Main Author: | |
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| Format: | Thesis Book |
| Language: | English |
| Published: |
[Place of publication not identified] :
[publisher not identified] ;
1994.
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| Subjects: | |
| Online Access: | http://proxy.library.tamu.edu/login?url=http://proquest.umi.com/pqdweb?did=741965301&sid=1&Fmt=2&clientId=2945&RQT=309&VName=PQD |
| Summary: | The synthesis of array specific Built-In Self Test (BIST) automata which can fully test an Iterative Logic Array (ILA) is proposed. These automata require a single control line, and, a clock. The size of an automaton can be very small if the tests in a test set repeat, and all the tests have One Repetition Length (ORL). Each test in C-test repeats and provides a minimum test set. These tests, however, repeat with different interval. The ORL is achieved by adjusting the repetition length of all the tests. This adjustment dramatically reduces the on-chip test generator size with a moderate increase in test set size. The probability distribution of the expected size of an automaton is also developed. The result is that these automata can be expected to test any array using a very small area. In addition, it can deliver these tests atspeed simply by using the emerging technology for both the functionality and the test circuitry. The automata is based on Linear Feedback Shift Register (LFSR). Typically, LFSR is used as a pseudo-random test pattern generator. This is modified so that the LFSR generates the test patterns required for testing the ILA followed optionally by pseudorandom patterns. The modified LFSR is called an Linear Finite State Machine (LFSM). Various factors that affect the size of the LFSM are discussed and methods for reducing it are described. In addition, we study the testing of one Dimensional (I-D) unilateral ILAs of combinational cells both under single faulty cell and multiple faulty cells and show that the ILAs with only boundary output are not C-testable under multiple faulty cells using the technique proposed by Cheng and Patel [1]. |
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| Item Description: | Vita. "Major Subject: Electrical Engineering". |
| Physical Description: | xi, 83 leaves : illustrations ; 28 cm. Issued also on microfiche from University Microfilms Inc. |
| Bibliography: | Includes bibliographical references. |