A method for finding the statically sensitized critical path in VLSI circuits /
accurately and/or more efficiently. Due to the huge number
| Main Author: | |
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| Format: | Thesis eBook |
| Language: | English |
| Published: |
[Place of publication not identified] :
[publisher not identified] ;
1995.
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| Subjects: | |
| Online Access: | Link to OAKTrust copy |
| Summary: | accurately and/or more efficiently. Due to the huge number algorithm. This algorithm uses some Automatic Test Pattern analysis is stopped at this point and the structural delay is analysis, is a path enumeration technique in which the as the critical paths of the circuit. Finding all the been found. In our timing analysis system, all circuits are before proceeding on to fill in the optional assignments of between signals. The second approach, called timing critical path of a circuit. The first is the block-oriented critical paths in a circuit is called the critical path deals with the development of the Static Timing Analysis Decision Making (PODEM) for simplicity. The algorithm delay and the delay found by the Static Timing Analysis deterministic sieves, trying to process and learn as much developed to process the increasingly difficult but smaller effective way is to attack this problem with a series of Generation (ATPG) concepts like imply and justify and also information as possible at each level before proceeding on to initially examined using the Static Timing Analysis input vector is simulated in order to find the sensitized is a significant difference between the longest structural levels, successively more sophisticated algorithms can be longest structural paths are examined, one path at a time, to of paths contained in some circuits, we feel that a more or very close to the longest structural delay, timing path-oriented algorithms that could solve this problem more paths. Most research until now has focused on finding single, problem. There are various methods at present to find the procedure, then the Dynamic Timing Analysis procedure is run procedure. If the longest statically-sensitizable path of proposed here also reduces the search space by completing all sections of the circuit until the longest true paths have see if one can be sensitized. A third approach, called technique in which delays along all paths are summed up that need to have these values for the path to be sensitized the backtracing and forward imply techniques of Path-Oriented the circuit being examined is found to have a delay equal to The longest sensitizable paths of a circuit are referred to the mandatory assignments of constant values to the gates the next level. Using the results obtained from the previous the other gates. timing simulation, is a vector-dependent method in which each to see if a tighter critical delay can be found. This thesis used as the critical delay of the circuit. However, if there without taking into account the functional relationships |
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| Item Description: | "Major subject: Electrical Engineering". Vita. |
| Physical Description: | x, 44 leaves : illustrations ; 28 cm. Also available online. Issued also on microfiche from Lange Micrographics. |
| Bibliography: | Includes bibliographical references. |