Design and implementation of a large integrated crossbar switch for a 256 x 256 x 8 interconnection network /
CMOS technology. The number of spare rows and columns in the
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| Format: | Thesis eBook |
| Language: | English |
| Published: |
[Place of publication not identified] :
[publisher not identified] ;
1995.
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| Subjects: | |
| Online Access: | Link to OAKTrust copy |
| Summary: | CMOS technology. The number of spare rows and columns in the contention. High packaging density, high speed, and I/O Crossbar switches provide the maximum possible bandwidth and crossbars have usually been limited to 64 x 64 ports. But defect-tolerant monolithic implementation in a 0.8 micron Distributed arbitration is provided for output port high bandwidth and/or low latency to increase overall system Index Terms - Crossbar switch 7 buffer, delay, interconnection networks, packet, clock cycle, arbitration, many applications such as shared memory multiprocessors, ATM Mbyte/sec bandwidth per port and a low message latency. minimization are achieved through the use of a large area, minimum possible latency of all interconnect structures. Due packaging, ball grid array. performance, priority, yield analysis, latch, decoder, performance. Large crossbar switches would be very useful in port full crossbar switch for use in multiprocessor and switch matrix is determined by a detailed yield analysis. switches and networks that carry visual information require telecommunications applications. The switch has a 50 these applications. We propose a new design for a 256 x 256 to the large area required for large switches, monolithic |
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| Item Description: | "Major subject: Electrical Engineering". In title, numerals are used. Vita. |
| Physical Description: | ix, 54 leaves : illustrations ; 28 cm. Also available online. Issued also on microfiche from Lange Micrographics. |
| Bibliography: | Includes bibliographical references. |