Implementation of a Header Processor for the PSi architecture /
a fiber optic medium, it is essential to have network
| Main Author: | |
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| Format: | Thesis eBook |
| Language: | English |
| Published: |
[Place of publication not identified] :
[publisher not identified] ;
1995.
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| Subjects: | |
| Online Access: | Link to OAKTrust copy |
| Summary: | a fiber optic medium, it is essential to have network and fabrication of this processor using 2 micron CMOS architecture is the Header Processor. A Header Processor was clock, based on a proposed architecture. Design, simulation clock. correct hardware layouts. A main component of this creates a lot of processing bottlenecks, thus reducing the designed at the transistor level and fabricated to test the high speed data transmission for computer networks. Fiber low error probability and gigabit transmission capacity. To optic communucations offer a combination of high bandwidth, possibilities of having a processor that will run on a 50 MHz processing components that can cope with these rates. The proposed for the processing of protocols, which transforms take full advantage of the data transmission rates offered by technology resulted in a processor that can run on a 2.35 MHz The fast development of optical communication technology in the high level specifications of protocols into effcient and the past decade has brought forth the possibility of very throughput. The PSi layer processing architecture was typical approach of using a software for protocol processing |
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| Item Description: | "Major subject: Electrical Engineering". Vita. |
| Physical Description: | x, 76 leaves : illustrations ; 28 cm. Also available online. Issued also on microfiche from Lange Micrographics. |
| Bibliography: | Includes bibliographical references. |