Design and optimization of a defect tolerant processor array /
analysis is done on the reconfiguration architecture. The
| Main Author: | |
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| Format: | Thesis eBook |
| Language: | English |
| Published: |
[Place of publication not identified] :
[publisher not identified] ;
1995.
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| Subjects: | |
| Online Access: | Link to OAKTrust copy |
| Summary: | analysis is done on the reconfiguration architecture. The Defect Tolerance, MIMD, Reconfiguration. In this thesis we design and optimization of a defect increase harvest rates. Keywords:Parallel Processing, of operations per memory word, is described. The of the interconnection network and yield by way of evaluating optimization includes trade-offs between number of processors, amount of local memory, performance and topology the performance for each parallel application. Yield tolerant MIMD processor array, for maximum performance per wafer area, targeted at applications that have a large number yield analysis considers the use of partially good cells to |
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| Item Description: | "Major subject: Electrical Engineering". Vita. |
| Physical Description: | viii, 32 leaves : illustrations ; 28 cm. Also available online. Issued also on microfiche from Lange Micrographics. |
| Bibliography: | Includes bibliographical references. |