An instruction issue mechanism for superscalar processors supporting multiple threads /
An instruction issue mechanism for superscalar processors
| Main Author: | |
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| Format: | Thesis eBook |
| Language: | English |
| Published: |
[Place of publication not identified] :
[publisher not identified] ;
1994.
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| Subjects: | |
| Online Access: | Link to OAKTrust copy |
| Summary: | An instruction issue mechanism for superscalar processors dependencies only before they are issued. This helps to mechanism is described. The processor model can handle a mechanism used in conjunction with multithreading offers the advantages of two of the most popular dynamic processor model developed to evaluate this instruction issue reservation stations with functional units to eliminate results obtained using this model show that this issue scheduling mechanisms: Tomasulo's algorithm and the Dispatch significantly increase the instruction issue rate. A significantly increases the throughput of the processor and Stack scheme. The instruction issue mechanism uses structural hazards. Instructions have to be checked for data supporting multiple threads is presented. This mechanism the overall resource utilization. units, and a variable instruction window size. Simulation variable number of threads, a variable number of functional |
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| Item Description: | "Major subject: Electrical Engineering". Vita. |
| Physical Description: | ix, 88 leaves : illustrations ; 28 cm. Also available online. |
| Bibliography: | Includes bibliographical references. |