Bit-serial RISC processing element for parallel processing /
25ns delay and a 65 mm floorplan size.
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| Format: | Thesis eBook |
| Language: | English |
| Published: |
[Place of publication not identified] :
[publisher not identified] ;
1994.
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| Subjects: | |
| Online Access: | Link to OAKTrust copy |
| Summary: | 25ns delay and a 65 mm floorplan size. advantageous to reduce space and power needs without attributed to the increase in the chip and memory transistor bitserial processing element and its associated on-chip clock can run at 40 MHZ. The processing chip is setup to be combination of new computer generation concepts and early computers simplicity. This is a desirable combination of data memory suitable for Fine-grain computing. The density. Now, chip density and complexity are approaching distinguished by the tremendous improvement in performance for the FPGA device is 56 input/output pins with a maximum higher potential to deliver scalable performance are poised memory capacity. Scalable architectures delivering a memory. The goal of this design effort was to obtain a minimum number of instructions and a small instruction and of light. This has prompted interset in scaling system over its predecessors. The improvements are mostly Over the past five decades, electronic computers have gone parallel computers. However, parallel computers having a processing element architecture of this thesis is a unique processing element has a two-phase clocking scheme where each programmed to a Field Programmable Gate Array (FPGA) device resources by the number of processors used, and enlarging sacrificing independent processor operation. The research stand-alone processor with communication capabilities using a sustained performance are desired in both sequential and techniques and architecture for a processing element designed that was conducted includes the design and development of a their physical limits due to limitations imposed by the speed through five generations of development. Each generation is to be used in scalable massively parallel systems where it is to become the new generation of electronic computers. The using Altera programming software. The minimum requirement |
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| Item Description: | "Major subject: Electrical Engineering". Vita. |
| Physical Description: | xi, 86 leaves : illustrations ; 28 cm. Also available online. |
| Bibliography: | Includes bibliographical references. |