Generation of Test Sequences for programmable logic array-based Finite State Machines /
(IUT). Many real-life machines have been considered, some
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| Format: | Thesis eBook |
| Language: | English |
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[Place of publication not identified] :
[publisher not identified] ;
1994.
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| Subjects: | |
| Online Access: | Link to OAKTrust copy |
| Summary: | (IUT). Many real-life machines have been considered, some a method to minimize the length of the test sequence. The also demonstrates that test sequences thus generated, are then used to construct the Test Sequence, using the combinatorial parts are implemented by a PLA, a Binary State combinatorial parts of the Finite State Machine, are cover a wide variety of faults. deterministic Finite State Machine. This thesis introduces edges. Since the partially enumerated Binary STG has a Entities on a network communicate with each other using Fault simulation experiments have been performed on these Finite State Machine. The test sequences generated, test For such states for which no UIO sequence exists, a unique for the core behavior of the implementation under test generate a Finite State Machine, with lesser number of If, during the synthesis of the Finite State Machine, the implemented by a PLA, it is possible, using the UIO is shown that this Binary STG may be partially enumerated to key to this approach is in the synthesis of the Finite length test sequences can result. The UIO sequence for each lesser number of edges, it is easy to see that shorter long and time-consuming to construct. A common method of Method, to generate shorter-length test sequences. It Method, W-Set Method, and the UIO Method. One drawback of model. Each of these methods assume that the of which model, commercial protocols. Fault coverage and protocols. Protocols are rigid specifications of rules responses generated to those inputs match the Shortest Path tour, going through every transition in the Signature Set is constructed. These UIO/signature sequences specification is a minimal, strongly connected, specification of a protocol is the Finite State Machine specification. The test sequence is constructed using a specifications, the results of which are also included. state in the partially enumerated Binary STG is constructed. State Machine. This approach proposes a that, if the Test Sequence to the implementation and verifying that the test sequences generated thus, is that the sequences are Testing of protocols have taken many directions. Most of the implementation to verify that that it indeed confirms these include application of a Test Sequence and checking to its specification. Checking is done by applying the Transition Graph, (Binary STG), can be easily realised. It unambiguous exchange of information. variety of methods, including, the Distinguishing Sequence which entities must follow to ensure proper operation and |
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| Item Description: | "Major subject: Computer Science". Vita. |
| Physical Description: | xiii, 162 leaves : illustrations ; 28 cm. Also available online. |
| Bibliography: | Includes bibliographical references. |