rdf-syntax-grammar
mods:
  schema location: http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
  title info:
    title: Improved test generation and verification using Recursive Learning
  name:
    name part: Reddy, Subodh M.
    name part: 1969-
    role:
      role term: creator
  type of resource: text
  genre: bibliography
  origin info:
    place:
      place term: xx
    date issued: 1994
    issuance: monographic
  language:
    language term: eng
  physical description:
    form: print
    extent: x, 55 leaves : illustrations ; 28 cm.
  abstract: Automatic test pattern generation (ATPG) for single stuck-at
  abstract: faults has become a highly mature science with the
  abstract: significant improvements made in the deterministic portion
  abstract: of the algorithm. D-algorithm, PODEM, FAN, TOPS, and
  abstract: SOCRATES were some of the complete test generators that were
  abstract: proposed in the past. Recently a new technique called
  abstract: Recursive Learning was proposed to solve the difficult
  abstract: problem of identifying redundant faults. This work proposes
  abstract: new ideas and techniques to improve any Recursive Learning
  abstract: based test generation. As the VLSI circuits increase in size
  abstract: automatic synthesis plays a significant role. Logic
  abstract: verification is another important research area which is
  abstract: receiving considerable attention. Formal logic verification
  abstract: is usefull in verifying and hence debugging automatic
  abstract: synthesis. A good logic verification tool, which consumes
  abstract: less memory and is faster is highly desirable, especially in
  abstract: a logic synthesis environment. This work presents a logic
  abstract: verification tool based on the exploitation of internal
  abstract: equivalencies and Ordered Binary Decision Diagrams (OBDDs).
  abstract: This approach effectively amal-gamates the structural and
  abstract: functional approaches to logic verification. OBDDs are
  abstract: highly sensitive to variable ordering and hence any OBDD
  abstract: based tool will be highly depependent on a, good variable
  abstract: order. The techniques presented here relatively decrease
  abstract: this dependency because of the fact, that only OBDDs with
  abstract: small sizes are required, but a good fariable order would
  abstract: definetly speed the process.
  note: by Subodh M. Reddy.
  note: Vita.
  note: "Major subject: Electrical Engineering".
  note: Includes bibliographical references.
  note: M.S. Texas A&M University 1994.
  subject:
    topic: Major electrical engineering
  record info:
    record content source: TXA
    record creation date: 960530
    record change date: 20151005050956.0
    record identifier: in00001298469