http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
Improved test generation and verification using Recursive Learning
Automatic test pattern generation (ATPG) for single stuck-at
faults has become a highly mature science with the
significant improvements made in the deterministic portion
of the algorithm. D-algorithm, PODEM, FAN, TOPS, and
SOCRATES were some of the complete test generators that were
proposed in the past. Recently a new technique called
Recursive Learning was proposed to solve the difficult
problem of identifying redundant faults. This work proposes
new ideas and techniques to improve any Recursive Learning
based test generation. As the VLSI circuits increase in size
automatic synthesis plays a significant role. Logic
verification is another important research area which is
receiving considerable attention. Formal logic verification
is usefull in verifying and hence debugging automatic
synthesis. A good logic verification tool, which consumes
less memory and is faster is highly desirable, especially in
a logic synthesis environment. This work presents a logic
verification tool based on the exploitation of internal
equivalencies and Ordered Binary Decision Diagrams (OBDDs).
This approach effectively amal-gamates the structural and
functional approaches to logic verification. OBDDs are
highly sensitive to variable ordering and hence any OBDD
based tool will be highly depependent on a, good variable
order. The techniques presented here relatively decrease
this dependency because of the fact, that only OBDDs with
small sizes are required, but a good fariable order would
"Major subject: Electrical Engineering".