rdf-syntax-grammar
mods:
  schema location: http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
  title info:
    title: Design and analysis of high performance multistage interconnection networks
  name:
    name part: Bhogavilli, Suresh K.
    role:
      role term: creator
  type of resource: text
  genre: bibliography
  origin info:
    place:
      place term: xx
    date issued: 1993
    issuance: monographic
  language:
    language term: eng
  physical description:
    form: print
    form: remote
    extent: xi, 92 leaves : illustrations ; 28 cm.
  abstract: Small switching elements are the key components of multistage interconnection networks (MINS) used in multiprocessors and in high speed switching fabrics for broad-band communication systems. The structure of their internal buffers, efficient design and utilization of the clock period are crucial factors in determining their performance. We begin with the study of various buffer allocation schemes that include m queue buffers with static and dynamic buffer allocation. The dynamic buffer allocation has the ability to adapt to variations in traffic patterns and are, therefore, shown to offer higher throughput and lower latency compared to static buffers. We prop a new buffer design, called dynamically allocated fully connected buffer, and s that it outperforms the existing designs. The applications considered to evaluate the buffer allocation schemes are asynchronous traffic that include data transmission and soft real time traffic that include voice and video. The advantages of non- Fl message selection over FIFO selection are also studied. Another important issue is the clock design in synchronous networks. The existing models assume that the clock period consists of two parts. The control messages are transferred between switching stages during the first part, and the actual d transfer takes place during the second part. We propose a new control design single queue MINs that reduces the duration of the clock period by making use output buffers and acknowledgments. We develop an analytical model to compare its performance with the existing designs reported in the literature. We validate on model with extensive simulation studies. Index Terms - Multistage interconnection networks, packet switching, static buffer allocation, dynamic buffer allocation, non-FIFO packet selection, soft real time traffic, performance analysis, throughput, delay, clock cycle.
  note: by Suresh K. Bhogavilli.
  note: "Major subject: Electrical Engineering".
  note: Vita.
  note: Also available online.
  note: M.S. Texas A&M University 1993.
  note: Includes bibliographical references.
  subject:
    topic: Major electrical engineering
  identifier: https://hdl.handle.net/1969.1/ETD-TAMU-1993-THESIS-B5755
  related item:
    location:
      url: https://hdl.handle.net/1969.1/ETD-TAMU-1993-THESIS-B5755
  record info:
    record content source: TXA
    record creation date: 960416
    record change date: 20220103113943.0
    record identifier: in00001296644