Cover Image

A bit-serial RISC architecture for MIMD computing /

The development of computer systems capable of parallel operation began as early as the 1950's. Originally driven by reliability considerations) subsequent parallel processing work was motivated by the desire to increase system performance. Parallel computation is achievable at several levels...

Full description

Bibliographic Details
Main Author:	Troy, Kevin Michael, 1962-
Format:	Thesis eBook
Language:	English
Published:	[Place of publication not identified] : [publisher not identified] ; 1993.
Subjects:	Major electrical engineering.
Online Access:	Link to OAKTrust copy

Similar Items

Bit-serial RISC processing element for parallel processing /
by: Haidar, Faisal A.
Published: (1994)

Error detection techniques in bit-serial multiplication /
by: Brosnan, Thomas Joseph
Published: (1983)

LSRM - a tool for logic simulation of RISC-based microprocessor /
by: Jiang, Xiaohua, 1961-
Published: (1993)

The TAMU '89 specialized RISC microprocessor /
by: Luk, Yau Tak, 1960-
Published: (1989)

A bit-serial floating point multiply/add architecture for signal processing applications /
by: Williams, Bertrand Jeffery, 1959-
Published: (1983)

A VLSI Cache RISC for the C language /
by: Chung, Chung-Ping, 1954-
Published: (1986)

GMSK two-bit differential detector performance enhancement with symmetric detection by using bit stuffing /
by: Suh, Young-Ho
Published: (1998)

Unequal error protection of subband coded bits /
by: Devalla, Badarinath, 1970-
Published: (1994)

Design, development, and analysis of processing elements for VLSI implemented MIMD computer system /
by: Waldo, Brandon Thayer, 1967-
Published: (1992)

Design and implementation of a 16-bit Reconfigurable Arithmetic Processor /
by: Janakiraman, Balaji
Published: (1993)

Parallel supercomputing in MIMD architectures /
by: Hord, R. Michael, 1940-
Published: (1993)

An 8-bit current mode ripple folding analog to digital converter /
by: Dinc, Huseyin, 1978-
Published: (2002)

Software implemented fault-tolernace on distributed-memory MIMD architectures /
by: Holland, Gavin D. (Gavin Douglas)
Published: (1995)

A 1.8V 10-bit 10MS/sec pipelined ADC /
by: Gunay, Zeki Sezgin, 1971-
Published: (1997)

An N-bit multi-cell encoded cellular neural network for multi-data processing /
by: Villareal, Samuel S.
Published: (1999)

Software based low bit rate speech codec using the Discrete Wavelet Transform /
by: Kadirvel, Sunitha
Published: (1997)

Evolution of double-dwell serial search acquisition with automatic threshold control /
by: Jung, Sung-Hyun, 1969-
Published: (1998)

A serially concatenated BCH-Turbo code scheme over an Additive White Gaussion Noise channel /
by: Ovalekar, Sameer V., 1974-
Published: (1997)

Parallel MIMD computation : the HEP supercomputer and its applications /
Published: (1985)

Parallel MIMD computation : the HEP supercomputer and its applications /
Published: (1985)

Study on the use of VLSI ASIC technology for generic power system computer relay architectures /
by: Faulkner, Kenneth Ray, 1969-
Published: (1994)

A CODEC for low to medium bit-rate video /
by: Taylor, Victor Byron, 1964-
Published: (1990)

Speech excitation encoding at low bit rates /
by: Kang, Sangwon, 1958-
Published: (1990)

Performance analysis using sequential detection in a serial multi-hop wireless sensor network /
by: Choi, Dae H.
Published: (2010)

VLSI RISC architecture and organization /
by: Furber, Stephen B. (Stephen Bo), 1953-
Published: (1989)

VLSI Risc Architecture and Organization.
by: Furber, S. B.
Published: (2017)

A parallel rendering algorithm for MIMD architectures /
by: Crockett, Thomas W.
Published: (1991)

Implementation of a Header Processor for the PSi architecture /
by: G, Vinod Nair
Published: (1995)

Data-parallel programming on MIMD computers /
by: Hatcher, Philip J.
Published: (1991)

Data-parallel programming on MIMD computers /
by: Hatcher, Philip J.
Published: (1991)

Design and simulation of an FPGA architecture /
by: Dong, Qiujie
Published: (1994)

Optimum bit-by-bit power allocation for minimum distortion transmission /
by: Karaer, Arzu, 1980-
Published: (2007)

Architecture-independent environment for developing engineering software on MIMD computers /
by: Valimohamed, Karim A.
Published: (1990)

Encoding serial data for Energy-Delay-Product and energy minimization /
by: Ekambavanan, Sasidharan
Published: (2010)

Geometric design of spherical serial chains with curvature constraints in the environment /
by: Tolety, Anurag Bharadwaj
Published: (2012)

Iterative cellular array multiplier using overlapped four-bit scanning technique and its application /
by: Kim, Wu Woan, 1955-
Published: (1990)

The development of a complex number computer.
by: Bird, Frank Stanley
Published: (1947)

A versatile computer model for the design and analysis of electric and hybrid vehicles /
by: Stevens, Kenneth Michael, 1971-
Published: (1996)

The MIPS-X RISC Microprocessor /
by: Chow, Paul, 1955-
Published: (1989)

Parallel Hough Transform for image processing on a Mesh of Trees architecture /
by: Cao, Yang, 1963-
Published: (1993)