rdf-syntax-grammar
mods:
  schema location: http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
  title info:
    non sort: A
    title: bit-serial RISC architecture for MIMD computing
  name:
    name part: Troy, Kevin Michael
    name part: 1962-
    role:
      role term: creator
  type of resource: text
  genre: bibliography
  origin info:
    place:
      place term: xx
    date issued: 1993
    issuance: monographic
  language:
    language term: eng
  physical description:
    form: print
    form: remote
    extent: xi, 85 leaves : illustrations ; 28 cm.
  abstract: The development of computer systems capable of parallel operation began as early as the 1950's. Originally driven by reliability considerations) subsequent parallel processing work was motivated by the desire to increase system performance. Parallel computation is achievable at several levels of hardware complexity. At the top is system-level hardware integration employing multiple independent micropro cessors. At a lower level, within the microprocessor, parallel operation is performed by pipelined and duplicate execution units. Programmable gate arrays capable of implementing multiple independent state machines are at the low end of the hardware complexity spectrum for parallel computation. The processing element architecture of this thesis is a unique combination of RISC design concepts, bit- serial computation and communication, and an MIMD organization implemented at a level of hardware complexity between the pipelined microprocessor and the programmable gate array. This is a desirable combination of techniques and architectures for a processing element designed for use in massively parallel systems where it is advantageous to reduce space and power needs without sacrificing independentprocessor operation. The data path and instruction set of the processing element are defined, as are the operating modes and states necessary to execute the instructions. The data path is translated from functional blocks to functioning circuit designs implemented in 2,u7n CMOS VLSI technology. Layouts are shown and the circuit models extracted from them are simulated by HSPICE. Circuit simulation results are then used to determine operational parameters such as maximum clock speed and execution and 1/0 rates. The area requirements of each component are discussed and a floor Plan of the processing element shows the relative size and placement of the components. Local memory requires 13mm', but the processing element requires only 2MM2 of the 15mm' total area. Maintaining the inde…
  note: by Kevin Michael Troy.
  note: "Major subject: Electrical Engineering".
  note: Vita.
  note: Also available online.
  note: M.S. Texas A&M University 1993.
  note: Includes bibliographical references.
  subject:
    topic: Major electrical engineering
  identifier: https://hdl.handle.net/1969.1/ETD-TAMU-1993-THESIS-T864
  related item:
    location:
      url: https://hdl.handle.net/1969.1/ETD-TAMU-1993-THESIS-T864
  record info:
    record content source: TXA
    record creation date: 960502
    record change date: 20220103114242.0
    record identifier: in00001291965