http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
a simulation based partitioning algorithm for ATPG
viii, 147 leaves : illustrations ; 28 cm.
The fast progressing of Integrated Circuit demands a highly efficient Automatic Test Pattern Generation algorithm. The problem in ATPG is how to minimize the huge redundant space in a highly reconvergent fanout circuit. This thesis presents an improved ATPG algorithm. Many techniques are combined into the algorithm to be able to identify the redundancy quickly. A circle concept is proposed to find the redundancy in a small search space instead of searching through the whole space. The PD concept combined with the simulation and improved implication procedures can discover necessary assignments, which is mandatory either to control the fault or to propagate the good/faulty difference, before we must make any decision. A complete implementation is shown in details. The experimental results taken from the ISCAS benchmark combinational circuits are compared to several ATPG algorithms.
"Major subject: Electrical Engineering".