| Abstract: | With electronic device speed approaching physical limits, parallel processing has become the next logical step toward achieving higher computing speeds. Parallel processors fall mainly into two categories, namely, message passing and shared memory. Shared Memory multiprocessors offer a simple programming model and have gained widespread popularity for general purpose programming needs. When the number of processors in a multiprocessor system increases, the interconnection network becomes more complex, and so the memory latency time also increases. Private cache memories offer an effective solution to this problem. However, the use of private cache memories brings with it the associated cache coherence problem. Many cache coherence schemes have been proposed and used for the shared memory multiprocessors over the past decade. There are several design and performance issues involved in the use of cache coherence schemes in multiprocessor systems. In this dissertation, we address the following issues related to design and application of cache coherent shared memory multiprocessors: (1) Performance evaluation of cache coherent multiprocessors. (2) Design of efficient interconnection networks to support cache coherence protocols. (3) Specification and verification of cache coherence protocols and (4) Efficient mapping of applications on cache coherent multiprocessors. Analytical models are developed for various cache coherent multiprocessor systems and are validated using an event driven simulation model. Since the analytical models run at least two orders of magnitude faster than the simulation programs, and are reasonably accurate, we prefer them over the later as an evaluation tool. A new network, called the Multistage Bus Network(MBN) is designed to support cache coherence protocols efficiently. The MBN consists of multiple stages of buses connected in a way similar to the Multistage Interconnection Network(MIN)... |
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