http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
Digital timing macromodeling for VLSI design verification
by Jeong-Taek Kong and David Overhauser.
Includes bibliographical references (pages 231-259) and index.
Kluwer international series in engineering and computer science ; SECS 201
Kluwer international series in engineering and computer science
VLSI, computer architecture, and digital signal processing