rdf-syntax-grammar
mods:
  schema location: http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
  title info:
    title: Digital timing macromodeling for VLSI design verification
  name:
    name part: Kong, Jeong-Taek
    name part: 1959-
    role:
      role term: creator
  name:
    name part: Overhauser, David
    name part: 1961-
  type of resource: text
  genre: bibliography
  origin info:
    place:
      place term: mau
    date issued: 1995
    issuance: monographic
  language:
    language term: eng
  physical description:
    form: print
    extent: xxi, 265 pages : illustrations ; 24 cm.
  note: by Jeong-Taek Kong and David Overhauser.
  note: Includes bibliographical references (pages 231-259) and index.
  subject:
    topic: Integrated circuits
    topic: Very large scale integration
    topic: Design and construction
    topic: Data processing
  subject:
    topic: Integrated circuits
    topic: Verification
    topic: Data processing
  subject:
    topic: Computer-aided design
  classification: TK7874 .K6437 1995
  classification: 621.39/5/011
  related item:
    title info:
      title: Kluwer international series in engineering and computer science ; SECS 201
  related item:
    title info:
      title: Kluwer international series in engineering and computer science
      part name: VLSI, computer architecture, and digital signal processing
  identifier: 0792395808 (alk. paper)
  identifier: 95015414
  record info:
    record content source: DLC
    record creation date: 950330
    record change date: 20151004051237.0
    record identifier: in00001264307