Design and implementation of a 16-bit Reconfigurable Arithmetic Processor /
Many evolving application areas , such as digital multimedia systems, artificial intelligence, image processing and high performance graphics systems, require complex arithmetic calculations to be performed within a limited number of clock cycles. These new applications usually involve manipulating...
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| Format: | Thesis eBook |
| Language: | English |
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[Place of publication not identified] :
[publisher not identified] ;
1993.
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| Online Access: | Link to OAKTrust copy |
| Summary: | Many evolving application areas , such as digital multimedia systems, artificial intelligence, image processing and high performance graphics systems, require complex arithmetic calculations to be performed within a limited number of clock cycles. These new applications usually involve manipulating a large amount of input data, often requiring iterative calculations, just as in digital signal processing (DSP) applications. A traditional Arithmetic and Logic Unit would take too many clock cycles. By employing some special purpose coprocessors, the number of clock cycles can be significantly reduced. The Reconfigurable Arithmetic Processor (RAP) described in [11] is one such processor and it uses a very simple and slow multiplier. Also the main processor is forced to sample the output of a much simpler operation at the maximum clock frequency which was determined by the worst case processing delay. This meant that for the simpler operations like addition and subtraction, the processor utilization is around 50%. The main objective of this thesis was to design, and implement a 16-bit recon figurable arithmetic processor, which can be more efficiently used in place of the Multiplier-Accumulator's [5] and the RAP used in [11]. As the demand for high speed processing has been increasing with expanding computer applications, the performance of any coprocessor has to be enhanced by using a multiplier as a key component. A very fast multiplier is used in this arithmetic processor which adopts the modified Booth's algorithm and Wallace method. For the adder/subtract unit, the carry-look-ahead scheme is adopted due to its simplicity and modularity that make it particularly adaptable to integrated circuit implementation. By using a slightly complex control circuit, the same carry-look-ahead adder is used for both the multiplier and the adder module thus saving 1/5 of the total chip real estate. Also a control circuit is designed to generate dedicated clocks of different frequencies for the different functions. In this thesis, the complete design, layout and simulations of the 16-bit arithmetic processor are presented. |
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| Item Description: | "Major Subject: Electrical Engineering". Vita. |
| Physical Description: | xii, 91 leaves : illustrations ; 28 cm. Also available online. |
| Bibliography: | Includes bibliographical references. |