http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
Automatic conformance testing of protocols implemented in software or hardware
xiii, 130 leaves : illustrations ; 28 cm
The complexity of today's distributed computing systems and networking requires the formulation of precise operations through the extensive use of protocols. Protocols implementations are required to undergo verification and validation of the implementation (conformance testing). Protocols of distributed systems and networks are extremely difficult to analyze because they involve intensive computing as well as tight bounds in meeting desired objectives. Previous conformance testing approaches suffer from either high computational complexity or low capability to detect errors. A protocol can be implemented as a piece of software as well as hardware (sequential circuits). The traditional UIO concept (unique input/output, for a test suite) for conformance testing of protocols and software is extended and new classes of UIO test suites are introduced. These UIO suites have better capabilities to check test cases and provide good flexibility in verification and validation of protocols. The test sequence generation is adaptive so that exhaustive checking is avoid. The proposed approach achieves shorter test sequences and no degradation of fault coverage. An approach to augment the implemented protocols (in sequential circuits) is proposed such that the cost of test generation and test application for sequential circuits is as low as the cost of test generation, evaluation and application for combinational circuits. 100% of fault coverage is achieved for the implemented protocols with only two extra inputs and less than 2.4% area overhead. The proposed approach is implemented using ASIC (application specific integrated circuit) and PLD (programmable logic device) design techniques. An approach is presented to automatically find the minimal number of test suites for fault diagnosis of protocols, software, or VLSI circuits. The proposed approach achieves an average reduction of 75% in the number of test suites for fault diagnosis without augmenting the original protocols, software, or VLSI circuits. The upper bound of the number of minimal test suites is twice of the number of the minimum test suites.