A tight clock synchronization technique for parallel processing systems /

Abstract: "In this paper, we present a tight clock synchronization scheme for large scale multiprocessor systems. In the proposed scheme, each clocking signal generated by the master clock source is replicated into two identical copies, and the twin signals are transmitted on two symmetric loo...

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Bibliographic Details
Main Author: Liu, Jyh-Charn
Other Authors: Hung, T.-C
Format: Book
Language:English
Published: College Station, Tex. : Texas A & M University, Computer Science Dept., [1991]
Series:Technical report (Texas A & M University. Computer Science Department) ; 91-035.
Subjects:
Description
Summary:Abstract: "In this paper, we present a tight clock synchronization scheme for large scale multiprocessor systems. In the proposed scheme, each clocking signal generated by the master clock source is replicated into two identical copies, and the twin signals are transmitted on two symmetric loops in opposite directions. Since the two loops are symmetric, the time difference between the two clocks' arriving times at a node is twice as long as the remaining time for the first arriving clock to reach the node that has an equal distance to the master node along the two transmission directions.
Thus, to cancel the clock skew between nodes, a local clock is issued in a node after the first received clock signal in that node is delayed by half of the phase difference between the two signals. To explore implementation issues in the proposed scheme, a Skew Cancellation Circuit (SCC), which is used to measure the phase difference between the clocking signals on the two loops, is designed with the combination of programmable delay element arrays and a phase detector. The floor-plan of SCC is implemented by the MAGIC VLSI layout tool based on the MOSIS CMOS 2[mu]m technology.
The double loop topology does not impose any constraints on the size and shape of the functional units, and is applicable to both tightly and loosely coupled systems. The function of SCC is studied by using extensive logic simulations."
Item Description:"August 1991."
Physical Description:28 leaves : illustrations ; 28 cm.
Bibliography:Includes bibliographical references.