Finite buffer analysis of multistage interconnection networks /
Abstract: "In this correspondence, we propose a design and analysis technique for a class of Multistage Interconnection Networks (MINs). This class of MINs have finite buffers at the input side of their switch elements and operate in a synchronous packet-switched mode. We first examine the im...
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| Format: | Book |
| Language: | English |
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College Station, Tex. :
Texas A & M University, Computer Science Dept.,
[1992]
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| Series: | Technical report (Texas A & M University. Computer Science Department) ;
92-008. |
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| Summary: | Abstract: "In this correspondence, we propose a design and analysis technique for a class of Multistage Interconnection Networks (MINs). This class of MINs have finite buffers at the input side of their switch elements and operate in a synchronous packet-switched mode. We first examine the important issue of different clock periods in the synchronous MIN analysis. Then we analyze our 'small cycle' design with a simple analytical model and compare the results with that of a somewhat standard 'big cycle' model that is currently used. The significant performance improvement of our model is shown based on various clock width, data width, and buffer length." |
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| Item Description: | "April 1992." |
| Physical Description: | 17 leaves : illustrations ; 28 cm. |
| Bibliography: | Includes bibliographical references. |