http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
Parallel FFT algorithms for cache based shared memory multiprocessors
Abstract: "Shared memory multiprocessors with cache require careful consideration of cache parameters while developing or implementing an algorithm to obtain optimal performance. Implementing synchronous algorithms on shared memory multiprocessors also needs synchronization steps to properly order the steps of execution in the algorithm. These synchronization steps are costly in terms of execution time and should be minimized. In this report, we study the implementation of some existing parallel FFT algorithms and analyze the number of cache misses based on the problem size, number of processors, cache size, and block size. We also propose a new FFT algorithm which minimizes the number of cache misses as well as the synchronization steps in the algorithm."
Supported in part by Texas ATP. 999903-165
Technical report (Texas A & M University. Computer Science Department) ; 93-022