rdf-syntax-grammar
mods:
  schema location: http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
  title info:
    title: Timing analysis of VLSI circuits using symbolic and visualization technics for practical applications
  name:
    name part: Shiau, Yan-Chyuan
    name part: 1957-
    role:
      role term: creator
  name:
    name part: Watson, Karan
    role:
      role term: degree supervisor.
  name:
    name part: Halverson, Don
    role:
      role term: degree committee member.
  name:
    name part: Lu, Mi
    role:
      role term: degree committee member.
  name:
    name part: Yen, John
    role:
      role term: degree committee member.
  name:
    name part: Texas A & M University
    role:
      role term: degree granting institution.
  type of resource: text
  genre: bibliography
  genre: Academic theses
  origin info:
    place:
      place term: xx
    date issued: 1992
    issuance: monographic
  language:
    language term: eng
  physical description:
    form: print
    extent: xvii, 146 leaves : illustrations ; 29 cm
  abstract: In this dissertation, we apply the linear RC delay modeling techniques to empirically model the timing delay in the CMOS VLSI circuits. The multi-dimensional function of various circuit combinations and device parameters is simplified to a two-dimensional model. This model estimates the timing delay of a circuit in terms of the generic RC delay and the rise/fall time delay of the input waveform. The auto-generator is developed to generate timing model for new process and technology. The Circuit Display Tool provide the capability for user to view the circuit topology from netlist in different level of display: Top-Level Circuit Display, SCC Display, and Cell Content Display. This tool not only shows user the content and control relations of cells in the design, but also displays the conducting situation for transistors in a cell. The active path can provide designers the actual signal path for selected object event in the circuit. The symbolic delay representation represents the delay of a sub-circuit with mathematical expression that shows the related components, such as transistors and nodes, which are deriving the subject output. User can accurately work on the critical portion of the circuit to improve the performance of the design. The design time can be significantly reduced through the help of this package.
  note: Typescript (photocopy).
  note: Vita.
  note: "Major subject: Electrical Engineering."
  note: Ph. D. Texas A & M University 1992
  note: Includes bibliographical references.
  subject:
    topic: Integrated circuits
    topic: Very large scale integration
    topic: Design
  subject:
    topic: Integrated circuits
    topic: Simulation methods
  subject:
    topic: Electric circuit analysis
  subject:
    topic: Major electrical engineering
  classification: ST 190
  identifier: http://proxy.library.tamu.edu/login
  related item:
    location:
      url: http://proxy.library.tamu.edu/login
  record info:
    record content source: TXA
    record creation date: 930326
    record change date: 20200904152637.0
    record identifier: in00001127397
    language of cataloging:
      language term: eng