http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
Timing analysis of VLSI circuits using symbolic and visualization technics for practical applications
xvii, 146 leaves : illustrations ; 29 cm
In this dissertation, we apply the linear RC delay modeling techniques to empirically model the timing delay in the CMOS VLSI circuits. The multi-dimensional function of various circuit combinations and device parameters is simplified to a two-dimensional model. This model estimates the timing delay of a circuit in terms of the generic RC delay and the rise/fall time delay of the input waveform. The auto-generator is developed to generate timing model for new process and technology. The Circuit Display Tool provide the capability for user to view the circuit topology from netlist in different level of display: Top-Level Circuit Display, SCC Display, and Cell Content Display. This tool not only shows user the content and control relations of cells in the design, but also displays the conducting situation for transistors in a cell. The active path can provide designers the actual signal path for selected object event in the circuit. The symbolic delay representation represents the delay of a sub-circuit with mathematical expression that shows the related components, such as transistors and nodes, which are deriving the subject output. User can accurately work on the critical portion of the circuit to improve the performance of the design. The design time can be significantly reduced through the help of this package.
"Major subject: Electrical Engineering."