rdf-syntax-grammar
mods:
  schema location: http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
  title info:
    title: Euro-DAC '92, European Design Automation Conference
    sub title: Euro-VHDL '92, Congress Centrum Hamburg, Hamburg, Germany, September 7-10, 1992
  title info:
    title: 1992 European Design Automation Conference
  name:
    name part: European Design Automation Conference (1992 : Hamburg, Germany)
    role:
      role term: creator
  name:
    name part: Gesellschaft für Informatik
  name:
    name part: IEEE Computer Society
    name part: Design Automation Technical Committee.
  type of resource: text
  genre: bibliography
  genre: conference publication
  genre: Conference papers and proceedings.
  origin info:
    place:
      place term: cau
    place:
      place term: Los Alamitos, Calif
    publisher: IEEE Computer Society Press
    date issued: ©1992
    date issued: 1992
    issuance: monographic
  language:
    language term: eng
  physical description:
    form: print
    extent: xviii, 765 pages : illustrations ; 28 cm
  table of contents: Asynchronous Design Techniques -- Path Breaker: A Tool for the Optimal Design of Speed Independent Asynchronous Controllers / Y. Mishra, S. D. Sherlekar and G. Venkatesh -- Asynchronous State Machine Synthesis Using Data Driven Clocks / F. Aghdasi -- Design of Delay Insensitive Circuits Using Multi-Ring Structures / J. Sparso, J. Staunstrup and M. Dantzer-Sorensen -- Design Methods -- DESB, A Functional Abstractor for CMOS VLSI Circuits / M. Laurentin, A. Greiner and R. Marbot -- Automatic Import of Custom Designs Into a Cell-Based Environment Using Switch-Level Analysis and Circuit Simulation / R. Stewart, V. Anjubault, P. Garcin and J. Benkoski -- Communication Based Logic Partitioning / M. Beardslee, B. Lin and A. Sangiovanni-Vincentelli -- Placement -- Parallel Algorithms for Slicing Based Final Placement / H. Spruth and G. Sigl -- Wolverines: Standard Cell Placement on a Network of Workstations / S. Mohan and P. Mazumder -- Genetic Algorithm for Macro Cell Placement / H. Esbensen -- Timing Issues in High-Level Synthesis -- Timing Models for High-Level Synthesis / V. Chaiyakul, A. C.-H. Wu and D. D. Gajski -- System Clock Estimation Based on Clock Slack Minimization / S. Narayan and D. D. Gajski -- Combined Topological and Functionality Based Delay Estimation Using a Layout-Driven Approach for High Level Applications / C. Ramachandran and F. J. Kurdahi -- Application of Formal Methods -- Correctness Verification of Concurrent Controller Specifications / M. T. L. Schaefer and W. U. Klein -- Design Verification Considering Manufacturing Tolerances by Using Worst-Case Distances / H. E. Graeb, C. U. Wieser and K. J. Antreich -- State Machine Abstraction from Circuit Layouts using BDD's: Applications in Verification and Synthesis / T. Kam and P. A. Subrahmanyam -- Verification of Digital Circuits Based on Formal Semantics of a Hardware Description Language / M. Mutz
  table of contents: Panel: Megatrend 2000 -- Women in Electronics!? -- Architectural Synthesis -- Integer Programming Approach to Instruction Implementation Method Selection Problem / M. Imai, A. Alomary, J. Sato and N. Hikichi -- Flexible Controlpath Microarchitecture Synthesis Based on Artificial Intelligence / A. J. W. M. ten Berg -- Performance Driven Interconnection Optimization for Microarchitecture Synthesis / Y.-M. Jiang, T.-F. Lee, T.-T. Hwang and Y.-L. Lin -- Timing Analysis and Verification -- Transient Simulation of Lossy Coupled Transmission Lines / S. Lin and E. S. Kuh -- Exact Solution of Timing Verification / E. Bolender and H. M. Lipp -- DynaTAPP: Dynamic Timing Analysis with Partial Path Activation in Sequential Circuits / P. Agrawal, V. D. Agrawal and S. C. Seth -- Delay Macromodels for the Timing Analysis of GaAs DCFL / A. I. Kayssi and K. A. Sakallah -- Module Generation -- ^ Efficient Methodology for Symbolic Compaction of Analog IC's with Multiple Symmetry Constraints / E. Felt, E. Charbon, E. Malavasi and A. Sangiovanni-Vincentelli -- PERFLEX: A Performance Driven Module Generator / S. Kim, R. M. Owens and M. J. Irwin -- P.SIZE: A Sizing Aid for Optimized Designs / N. Azemard, V. Bonzom and D. Auvergne -- Combinational Logic Synthesis -- Boolean Matching in Logic Synthesis / H. Savoj, M. J. Silva, R. K. Brayton and A. Sangiovanni-Vincentelli -- ALU Synthesis from HDL Descriptions to Optimized Multi-Level Logic / F. Buijs -- Calculation of the Rademacher-Walsh Spectrum from a Reduced Representation of Boolean Functions / B. J. Falkowski, I. Schafer and M. A. Perkowski -- Systems Engineering and Mechatronics I -- High-Level Synthesis in a Rapid-Prototype Environment for Mechatronic Systems / N. Wehn, H.-J. Herpel, T. Hollstein, P. Poechmueller and M. Glesner -- ^
  table of contents: Top-Down Physical Design -- On the Intrinsic Rent Parameter and Spectra-Based Partitioning Methodologies / L. Hagen, A. B. Kahng, F. J. Kurdahi and C. Ramachandran -- Embedded Pin Assignment for Top-Down System Design / T. Pfortner, S. Kiefl and R. Dachauer -- Chip Assembly in the PLAYOUT VLSI Design System / K. Glasmacher and G. Zimmermann -- FPGA Based Design -- Maximal Reduction of Lookup-Table Based FPGAS / K.-C. Chen and J. Cong -- New Approach to the Decomposition of Incompletely Specified Multi-Output Functions Based on Graph Coloring and Local Transformations and Its Application to FPGA Mapping / W. Wan and M. A. Perkowski -- Systems Engineering and Mechantronics II -- Towards a Requirements Definition, Specification and System Design Environment / K. D. Muller-Glaser, J. Bortolazzi and Y. Tanurhan -- Test Strategies -- SIESTA: A Multi-Facet Scan Design System / S. Narayanan, C. Njinda, R. Gupta and M. Breuer -- Tackling Cost Optimization in Testable Design by Forward Inferencing / M. Kraak and R. H. J. M. Otten -- Multi-Level Testability Assistant for VLSI Design / M. Bombana, G. Buonanno, P. Cavalloro, D. Sciuto and G. Zaza -- FSM Design -- Efficient Constrained Encoding for VLSI Sequential Logic Synthesis / C.-J. Shi and J. A. Brzozowski -- ROM-Based Finite State Machines with PLA Address Modifiers / T. Luba, K. Gorski and L. B. Wronski -- Minimal Area Merger of Finite State Machine Controllers / D. Mukherjee, M. Pedram and M. Breuer -- Routing -- Routing Algorithms for Multi-Chip Modules / J. Lienig, K. Thulasiraman and M. N. S. Swamy -- Fast Multilayer General Area Router for MCM Designs / K.-Y. Khoo and J. Cong -- Distributed Routing System for Multilayer SOG / T. Shimamoto, H. Hane, I. Shirakawa, S. Tsukiyama, S. Shinoda, N. Yui and N. Nishiguchi -- Test Generation
  table of contents: Cross-Fertilizing FSM Verification Techniques and Sequential Diagnosis / G. Cabodi, P. Camurati, F. Corno, P. Prinetto and M. Sonza Reorda -- Generation of Deterministic Test Patterns by Minimal Basic Test Sets / A. B. Kunzmann -- MILEF: An Efficient Approach to Mixed Level Automatic Test Pattern Generation / U. Glaser and H. T. Vierhaus -- Automatic Partitioning for Deterministic Test / D. Crestani, A. Aguila, M.-H. Gentil, P. Chardon and C. Durante -- Scheduling and Allocation -- Automatic Module Allocation in High Level Synthesis / P. Gutberlet, J. Muller, H. Kramer and W. Rosentiel -- Heuristics for Branch-and-Bound Global Allocation / J. Septien, D. Mozos, F. Tirado, R. Hermida and M. Fernandez -- Neural Network Based Algorithm for the Scheduling Problem in High-Level Synthesis / M. Nourani, C. A. Papachristou and Y. Takefuji -- Topological Optimization in Routing -- Optimal Channel Pin Assignment with Multiple Intervals for Building Block Layout / T. Koide, S. Wakabayashi and N. Yoshida -- Crossing Distribution / D. C. Wang and C. B. Shung -- Topology Optimization Techniques for Power/Ground Networks in VLSI / K.-H. Erhard, F. M. Johannes and R. Dachauer -- Design for Testability -- Performance Driven Generator for Efficient Testable Conditional-Sum-Adders / B. Becker and P. Molitor -- Time Optimal Robust Path-Delay-Fault Self-Testable Adder / B. Becker and R. Drechsler -- Design for Testability View on Placement and Routing / D. Feltham, J. Khare and W. Maly -- High Level Synthesis and Test -- Generating Pipelined Datapaths Using Reduction Techniques to Shorten Critical Paths / D. A. Lobo and B. M. Pangrle -- Harmonic Scheduling of Linear Recurrences for Digital Filter Design / H. Wang, N. Dutt and A. Nicolau -- SYNTEST: An Environment for System-Level Design for Test / H. Harmanani, C. Papachristou, S. Chiu and M. Nourani -- Circuit-Level Analysis
  table of contents: Fast and Accurate Characterization Method for Full-CMOS Circuits / R. P. Llopis and H. G. Kerkhoff -- Exact Analytic Technique for Simulating Uniform RC Lines / J. S. Roychowdhury, A. R. Newton and D. O. Pederson -- Dynamic Scheduling Algorithm for the Simulation of MOS and Bipolar Circuits Using Waveform Relaxation / W. Rissiek and W. John -- Fault Simulation -- SPADES: A Simulator for Path Delay Faults in Sequential Circuits / I. Pomeranz, L. N. Reddy and S. M. Reddy -- Fast Fault Simulation in Combinational Circuits: An Efficient Data Structure, Dynamic Dominators and Refined Check-Up / B. Becker, R. Hahn and R. Krieger -- Linear Time Fault Simulation Algorithm Using a Content Addressable Memory / N. Ishiura and S. Yajima -- SEESIM -- A Fast Synchronous Sequential Circuit Fault Simulator with Single Event Equivalence / C. P. Wu, C. L. Lee and W. Z. Shen -- System and Information Modelling -- On Modeling Integrated Design Environments / C. Hubel, D. Ruland and E. Siepmann -- Information Modelling of Folded and Unfolded Design / G. Scholz and W. Wilkes -- Design Error Detection and Location -- Locating Logic Design Errors via Test Generation and Don't-Care Propagation / S.-Y. Kuo -- New Design Error Modeling and Metrics for Design Validation / S. Kang and S. A. Szygenda -- Testing Using Current Profiles -- Random Current Testing for CMOS Logic Circuits by Monitoring a Dynamic Power Supply Current / H. Tamamoto, H. Yokoyama and Y. Narita -- Test Generation for I[subscript DDQ] Testing and Leakage Fault Detection in CMOS Circuits / U. Mahlstedt, M. Heinitz and J. Alt -- Unifying Data for CAD-Frames and Testing -- Design Assistance for CAD Frameworks / J. C. Lopez, M. F. Jacome and S. W. Director -- Unifying Tool, Data and Process Flow Management / M. Rumsey and C. Farquhar -- ANT -- A Test Harness for the NELSIS CAD System / C. A. Schot, M. N. Sim and P. M. Kist -- ^ Tools Exploiting Concurrency
  table of contents: Finite State Machine Verification on MIMD Machines / N. Kumar and R. Vemuri -- Parallel Asynchronous Discrete Event Logic Simulation in ELSA / D. K. Arvind -- Approach to Multi-Paradigm Controller Synthesis from Timing Diagram Specifications / W.-D. Tiedemann -- Benchmark Experiments in Testing -- Cellular Scan Test Generation for Sequential Circuits / C. Gloster, Jr. and F. Brglez -- Experiments on the Synthesis and Testability of Non-Scan Finite State Machines / M. Pabst, T. Villa and A. R. Newton -- Quantitative Measure of Robustness for Delay Fault Testing / W. Mao and M. D. Ciletti -- Frameworks and Design Environments -- JESSI Common Framework Design Management -- The Means to Configuration and Execution of the Design Process / D. C. Liebisch and A. Jain -- Design of a Tool Interface for Integrated CAD-Environments / U. Hunzelmann, W. Wilkes and G. Schlageter -- Representing the Hardware Design Process by a Common Data Schema / M. Brielmann and E. Kupitz -- Generic Systems for Statistical Circuit Design -- GOSSIP -- A Generic System for Statistical Circuit Design / L. J. Opalski and M. A. Styblinski -- Generic Software System for Drift Reliability Optimization of VLSI Circuits / M. Huang and M. A. Styblinski -- PAR-APLAC: Parallel Circuit Analysis and Optimization / E. Pajarre, T. Ritoniemi and H. Tenhunen -- Role of CAD in the 90's -- Design Technology Research for the Nineties: More of the Same? / H. De Man -- Challenges for CAD in Computer Development in the 1990's / G. Dedie -- Electronic System Design -- Tools and Methodology to Meet the Productivity Challenge / R. Davies -- Special Session: EDA Standards -- The State of the Art -- Opening of Euro-VHDL/VHDL In High-Level Synthesis -- Compiling VHDL into a High-Level Synthesis Design Representation / P. Eles, K. Kuchcinski, Z. Peng and M. Minea -- Flexible Timing Specification in a VHDL Synthesis Subset / A. Stoll, J. Biesenack and S. Rumler
  table of contents: Semantics and Synthesis of Signals in Behavioral VHDL / L. Ramachandran, F. Vahid, S. Narayan and D. D. Gajski -- VHDL-Related Methods -- Integration of SDL and VHDL for High-Level Digital Design / O. Pulkkinen and K. Kronlof -- Using VHDL for Simulation of SDL Specifications / B. Lutter, W. Glunz and F. J. Rammig -- VHDL and Fuzzy Logic If-Then Rules / A. Zamfirescu and C. Ussery -- Panel: Implementation of VHDL Simulation -- Design Experience Using VHDL -- Experiences and Issues in VHDL-Based Synthesis / S. E. Lim, D. C. Hendry and P. F. Yeung -- VHDL for High Speed Desktop Video ICs -- Experience with Replacement of Other Simulator / M. Jacobsen and W. Nebel -- Design of Complex Systems with a VHDL Based Methodology / S. Amadori and P. Coerezza -- VHDL Standardization '92 (Invited Papers) -- 1992 VHDL Standardization Overview / M. Shahdad -- Analysis of User Requirements / J. Rouillard -- VHDL 1076-1992 Languages Changes / A. Guyler -- VHDL-Forum for CAD in Europe: VHDL in the European CAD Integration Project (ECIP) -- Synchronous Design in VHDL / A. Debreil and P. Oddo -- Towards a Common RT-Level Subset of VHDL / W. Ecker -- Selected Aspects of Component Modeling / A. Pawlak -- Interest of a VHDL Native Environment / J. L. Giordana -- Multi-Kernel Simulation Description within VHDL / C. Oczko and M. W. Nitsche -- VHDL Intermediate Format Standardization Activity: Status and Trends / A. Fonkoua and J. Rouillard -- Panel: VHDL-Forum for CAD in Europe: Industrial Use of VHDL in ASIC Design -- Formal Verification in VHDL -- Temporal Verification of Behavioral Descriptions in VHDL / D. Boussebha, N. Giambiasi and J. Magnier -- Providing a VHDL-Interface for Proof Systems / G. Umbreit -- Future of VHDL Standardization (Invited Papers) -- Towards a Standard VHDL Synthesis Package / P. L. Harper and K. Scott
  table of contents: VHDL Analog Extensions: Process, Issues and Status / R. Cottrell, K. Nolan and M. Brown -- VHDL Intermediate Form Standardization / M. Brown -- Use of VHDL in Synthesis -- Subtype Concept of VHDL for Synthesis Constraints / W. Ecker and S. Marz -- Synthesis of VHDL Arrays on RAM Cells / C. Berthet, J. Rampon and L. Sponga -- Using VHDL for Datapath Synthesis / V. Olive, R. Airiau, J. M. Berge and A. Robert -- Closing of Euro-VHDL/VHDL Language Analysis -- Challenges in the Analysis of VHDL / D. B. Bernstein, D. Charness and R. Farrow -- Evaluation Criteria of HDLs: VHDL Compared to Verilog, UDL/I & M / S. Maginot -- Design Cube -- A New Model for VHDL Designflow Representation / W. Ecker and M. Hofmeister.
  note: sponsored by Gesellschaft für Informatik e.V. (GI), IEEE Computer Society Technical Committee on Design Automation (IEEE/DATC) ; cosponsored by Association for Computing Machinery (ACM/SIGDA) [and others].
  note: Cover title: 1992 European Design Automation Conference.
  note: "IEEE Computer Society Press order number 2780"--Title page verso.
  note: "IEEE catalog number 92CH3126-0"--Title page verso.
  note: "ACM order number 477921"--Title page verso.
  note: Includes bibliographical references and index.
  subject:
    topic: Electronic digital computers
    topic: Circuits
    topic: Design
    genre: Congresses
  subject:
    topic: Electronic circuit design
    topic: Data processing
    genre: Congresses
  subject:
    topic: Computer-aided design
    genre: Congresses
  subject:
    topic: VHDL (Computer hardware description language)
    genre: Congresses
  subject:
    topic: Conception assistée par ordinateur
    genre: Congrès
  subject:
    topic: VHDL (Langage de description de matériel informatique)
    genre: Congrès
  subject:
    topic: Computer-aided design
  subject:
    topic: Electronic circuit design
    topic: Data processing
  subject:
    topic: Electronic digital computers
    topic: Circuits
    topic: Design
  subject:
    topic: VHDL (Computer hardware description language)
  subject:
    topic: VHDL
    topic: Formal computer system verification
    topic: CAD
    topic: Computer Aided Design
    topic: EDA standards
    topic: Fault simulation
    topic: Circuit design
    topic: FSM
    topic: VLSI
    topic: CMOS
    topic: Concurrent controllers
  classification: TK7888.4 .E97 1992
  classification: 621.39/2
  classification: PM 72
  classification: PM 722(V20)
  identifier: 0818627824
  identifier: 9780818627828
  identifier: 0818627808
  identifier: 9780818627804
  identifier: 0818627816
  identifier: 9780818627811
  identifier: 0897914910
  identifier: 9780897914918
  identifier: 0897914929
  identifier: 9780897914925
  identifier: 91078306
  identifier: http://ieeexplore.ieee.org/servlet/opac
  identifier: http://www.acm.org/pubs/contents/proceedings/dac/159754/
  related item:
    location:
      url: http://ieeexplore.ieee.org/servlet/opac
  related item:
    location:
      url: http://www.acm.org/pubs/contents/proceedings/dac/159754/
  record info:
    record content source: DLC
    record creation date: 930316
    record change date: 20230630112358.0
    record identifier: in00001091812
    language of cataloging:
      language term: eng