| Abstract: | A model for a comprehensive yield analysis of WSI processor arrays has been developed. The yield model is partitioned into three logically well-separated submodels: failures, testing and embedding. Failures are clearly divided into physical failures (defects) and logical failures (faults), and the relation is defined by the sensitivity of faults to defects. The completeness of cell-level testing is reflected in the yield model as a reduction coefficient, the probability that all the processor cells in the array are good. A new hierarchical definition of fault coverage is introduced to remove drawbacks in the traditional definition. A specific embedding program for two-dimensional arrays is designed based on the divide and conquer strategy, and then Monte Carlo simulation is conducted to show the effects of key parameters in the model. The embedding probability is defined from the subunit embedding probability and combining probability. Finally, those results are integrated successfully into a mathematical expression. The equation is used to study possible approaches for higher wafer yield. |
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